FIG. 1a represents a conventional switched capacitor circuit and FIG. 1b illustrates a timing diagram for same. In the timing diagram a two phase clock (.phi.1 and .phi.2) drives a plurality of switches within a first switched capacitor branch, containing C1, and within a second switched capacitor branch, containing C2. The switches are designated by their respective driving clock phase. As employed herein, all switches designated (.phi.1) close when this phase is high and open when this phase is low. All switches designated (.phi.2) close when this phase is high and open when this phase is low. In a typical embodiment each of the switches is an electronic device, such as a FET. One particularly useful application for the circuit of FIG. 1a is as a component of an analog-to-digital converter (A/D).
In operation, and beginning with (.phi.2), amplifier A stores charge on C1, the output of amplifier B and the input of amplifier C are disconnected from the circuit, capacitor C2 is reset to a ground potential, and the integration capacitor CF is reset by the switch connected in parallel therewith. At (.phi.1), C1 is connected to the summing junction of amplifier C, and the output of amplifier B is also coupled to the summing junction of amplifier C through C2. During (.phi.1) both C1 and C2 discharge into the feedback capacitor CF and their respective outputs are summed.
A problem that arises during the use of this conventional circuit is that the output of amplifier (B) settles during .phi.1 and, also during .phi.1, the output of amplifier B drives amplifier C. That is, the output signals of both amplifiers B and C must settle for some finite amount of time during .phi.1, although the settling of amplifier C cannot occur until after amplifier B has settled. The sequential settling requirement precludes the use of the circuit of FIG. 1 in an A/D that is required to operate at a high rate, such as 20 million conversions/sec, and at a high conversion accuracy, such as greater than 12 bit accuracy.
As considered herein, the term "settling" refers to the characteristic of an amplifier output signal to asymptotically approach a steady state value after a change in the input to the amplifier. Related to this definition is a definition of an amplifier "settling time", which refers to an amount of time required for the amplifier output signal to approach the steady state value, to within some desired tolerance, after a change in the input to the amplifier.
One conventional approach to overcoming this problem includes the use of half-clock cycle delay buffers to isolate amplifier B from amplifier C. Each buffer contains a high slew rate, high bandwidth, high power amplifier. However, the error resulting from the increased power, and complexity, make this approach undesirable.
It is therefore an object of the invention to provide a method, and circuitry for practicing the method, for coupling two input signals to an output node, without requiring the use of two serially coupled amplifiers or additional delay amplifiers.